In recent years, the development of electronic paper has been promoted in companies, universities, etc. Applied fields expected to utilize electronic paper have been proposed, including a variety of fields, such as electronic books, a sub-display for mobile terminal equipment, and a display part of an IC card. One promising methods of electronic paper is that which uses cholesteric liquid crystal. A cholesteric liquid crystal has excellent characteristics, such as the ability to semipermanently hold a display (memory property), vivid color display, high contrast, and high resolution.
Cholesteric liquid crystals are also referred to as chiral nematic liquid crystals, which form a cholesteric phase in which molecules of the nematic liquid crystal are in the form of a helix by adding a comparatively large amount (a few tens of percent) of additives (chiral material) having chiral property to the nematic liquid crystal.
FIG. 1A and FIG. 1B are diagrams explaining the states of the cholesteric liquid crystals. As illustrated in FIG. 1A and FIG. 1B, a display element 10 that utilizes cholesteric liquid crystals has an upper side substrate 11, a cholesteric liquid crystal layer 12, and a lower side substrate 13. Cholesteric liquid crystals have a planar state in which incident light is reflected as illustrated in FIG. 1A and a focal conic state in which incident light is transmitted as illustrated in FIG. 1B, and theses states are maintained stably even if there is no electric field.
In the planar state, light having a wavelength in accordance with the helical pitch of liquid crystal molecules is reflected. A wavelength λ at which reflection is maximum is expressed by the following expression where n is an average refractive index and p is a helical pitchλ=n·p. 
On the other hand, a reflection band Δλ differs considerably depending on a refractive index anisotropy Δn of liquid crystal.
In the planar state, a “bright” state can be displayed because incident light is reflected. On the other hand, in the focal conic state, a “dark” state, i.e., black can be displayed because light having passed through the liquid crystal layer is absorbed by a light absorbing layer provided under the lower side substrate 13.
Next, a method of driving a display element that utilizes cholesteric liquid crystals is explained.
FIG. 2 illustrates an example of a voltage-reflection characteristic of general cholesteric liquid crystals. The horizontal axis represents a voltage value (V) of a pulse voltage to be applied with a predetermined pulse width between electrodes that sandwich cholesteric liquid crystals and the vertical axis represents a reflectivity (%) of cholesteric liquid crystals. A curve P of a solid line illustrated in FIG. 2 represents the voltage-reflectivity characteristic of cholesteric liquid crystals when the initial state is the planar state and a curve FC of a broken line represents the voltage-reflectivity characteristic of cholesteric liquid crystals when the initial state is the focal conic state.
In FIG. 2, if a predetermined high voltage VP100 (for example, ±36 V) is applied between the electrodes to generate a relatively strong electric field in the cholesteric liquid crystal, the helical structure of the liquid crystal molecules is undone completely and a homeotropic state is brought about, where all of the molecules align in the direction of the electric field. Next, when the liquid crystal molecules are in the homeotropic state, if the applied voltage is reduced rapidly from VP100 to a predetermined low voltage (for example, VF0=±4 V) to reduce the electric field in the liquid crystal almost to zero, the helical axis of the liquid crystal becomes perpendicular to the electrode and the planar state is brought about, where light in accordance with the helical pitch is reflected selectively.
On the other hand, if a predetermined low voltage VF100b (for example, ±24 V) is applied between electrodes to generate a relatively weak electrical field in the cholesteric liquid crystal, a state is brought about where the helical structure of the liquid crystal molecules is not undone completely. In this state, if the applied voltage is reduced rapidly from VF100b to the low voltage VF0 to rapidly reduce the electric field in the liquid crystal almost to zero, or a strong electric field VP100 is removed gradually, the helical axis of the liquid molecule becomes parallel with the electrode and the focal conic state where incident light is transmitted is brought about.
Further, if the electric field is removed rapidly by applying an electric field of intermediate strength, the planar state and the focal conic state coexist in a mixed condition and it is possible to display a gradation.
A display is produced by utilizing the above-mentioned phenomena.
The principles of a driving method based on the voltage response characteristic described above are explained with reference to FIG. 3A to FIG. 3C.
FIG. 3A illustrates the pulse response characteristic when the pulse width of a voltage pulse is a few tens of ms, FIG. 3B illustrates the pulse response characteristic when the pulse width of a voltage pulse is 1.88 ms, and FIG. 3C illustrates the pulse response characteristic when the pulse width of a voltage pulse is 0.94 ms. In each figure, a voltage pulse to be applied to a cholesteric liquid crystal is illustrated on the upper side and the voltage-reflectivity characteristic is illustrated on the lower side, and the horizontal axis represents a voltage (V) and the vertical axis represents reflectivity (%). As a well known drive pulse of a liquid crystal, a voltage pulse is a combination of a positive polarity pulse and a negative polarity pulse in order to prevent the liquid crystal from deteriorating due to polarization.
As illustrated in FIG. 3A, when the pulse width is great, as illustrated by the solid line, if the initial state is the planar state, the state changes into the focal conic state when the voltage is raised to a certain range and if the voltage is further raised, the state changes into the planar state again. As illustrated by the broken line, when the initial state is the focal conic state, the state gradually changes into the planar state as the pulse voltage is raised.
When the pulse width is great, the voltage pulse, at which the state changes into the planar state whether the initial state is the planar state or the focal conic state, is ±36 V, and therefore, the initialization pulse is set to a pulse of ±36 V as illustrated in FIG. 3A. With a pulse voltage in the middle of this range, the state is such that the planar state and the focal conic state coexist in a mixed condition, and therefore, a gradation can be obtained.
On the other hand, when the pulse width is 1.88 ms as illustrated in FIG. 3B, when the initial state is the planar state, the reflectivity remains unchanged when the voltage pulse is about 10 V, however, at higher voltages, the state is such that the planar state and the focal conic state coexist in a mixed condition, and therefore, the reflectivity is reduced. The amount of reduction in reflectivity increases as the voltage is increased, however, when the voltage is increased than 36 V, the amount of reduction in reflectivity becomes constant. This is also the same when the initial state is a state where the planar state and the focal conic state coexist in a mixed condition. Because of this, when the initial state is the planar state, if a voltage pulse having a pulse width of 1.88 ms and a pulse voltage of about 20 V is applied once, the reflectivity is reduced by a certain amount. In this manner, in the state where the planar state and the focal conic state coexist in a mixed condition and the reflectivity is reduced by a small amount, if a voltage pulse having a pulse width of 1.88 ms and a pulse voltage of about 20 V is further applied, the reflectivity is reduced further. If this is repeated, the reflectivity is reduced to a predetermined value. As described above, when the pulse width is 1.88 ms, the reflectivity (gradation) changes by a voltage pulse of about 20 V, but does not change by a voltage pulse of about 10 V, and therefore, the pulse in FIG. 3B is set to ±18.6 V when ON, and to ±9.3 V when OFF.
As illustrated in FIG. 3C, when the pulse width is 0.94 ms, the reflectivity is reduced when a voltage pulse is applied in a manner similar to that when the pulse width is 1.88 ms, however, the amount of reduction in reflectivity is smaller compared to the case where the pulse width is 1.88 ms.
From the above, it can be thought that if a pulse of 36 V having a great width is applied, the planar state is brought about and if a gradation pulse of about ten-something to 20 V is applied, a state where the planar state and the focal conic state coexist in a mixed condition is brought about and the reflectivity is reduced, and the amount of reduction in reflectivity depends on the cumulative time of the gradation pulse.
As to the multi-gradation display method by cholesteric liquid crystal, there have been proposed various driving methods. The method of driving a multi-gradation display by cholesteric liquid crystal is divided into a dynamic driving method and a convention driving method.
Japanese Laid-open Patent Publication No. 2001-228459 describes a dynamic driving method. Y.-M. Zhu, D-K. Yang, Cumulative Drive Schemes for Bistable Reflective Cholesteric LCDs, SID 98 DIGEST, pp 798-801, 1998 describes the conventional driving method.
Japanese Laid-open Patent Publication No. 2000-147466 and Japanese Laid-open Patent Publication No. 2000-171837 describe a method of driving a fast-forward mode that applies resetting to the focal conic state.
When a gradation is set by utilizing the cumulative time by the conventional driving method, there can be thought a method in which the pulse width is varied, in addition to a method of adjusting the number of times of application of a short pulse, as described above. The method of varying the pulse width has an advantage over the method of adjusting the number of times of application of a short pulse from the standpoint of suppression of power consumption. Hereinafter, a method of setting a gradation by varying the pulse width to vary the cumulative time is referred to as a pulse width modulation (PWM) method.
Japanese Laid-open Patent Publication No. 04-62516 describes a configuration in which a positive polarity pulse and a negative polarity pulse having different pulse widths are applied in a liquid crystal display device, although the display device does not use a cholesteric liquid crystal.
FIG. 4 is a diagram explaining an example of a writing method in which a gradation is written by varying the cumulative application time of a pulse in combination of both the number of times of application of a pulse and the pulse width.
In a first step, initialization processing is performed in which a high voltage pulse of ±36 V having a pulse width of 40 ms is applied to all of the pixels and all of the pixels are brought into the planar state.
In a second step, processing to write a gradation is performed. The second step is divided into three sub-steps, that is, first, second and third sub-steps, and the first sub-step is further divided into three sub-steps, that is, 1-1, 1-2 and 1-3 and the second sub-step is further divided into three sub-steps, i.e., 2-1, 2-2 and 2-3.
In the sub-step 1-1, a pulse of ±18.6 V having a pulse width of 1.88 ms is applied, in the sub-step 1-2, a pulse of ±18.6 V having a pulse width of 0.94 ms is applied, and in the sub-step 1-3, a pulse of ±18.6 V having a pulse width of 0.47 ms is applied. The three sub-steps 1-1, 1-2 and 1-3 can be performed continuously when one scan line is selected or can be performed as different frames. Similarly, in the sub-step 2-1, a pulse of ±18.6 V having a pulse width of 2.82 ms is applied, in the sub-step 2-2, a pulse of ±18.6 V having a pulse width of 1.41 ms is applied, and in the sub-step 2-3, a pulse of ±18.6 V having a pulse width of 0.94 ms is applied. The three sub-steps 2-1, 2-2 and 2-3 can be performed continuously when one scan line is selected or can be performed as different frames. In the third sub-step 3, a pulse of ±18.6 V having a pulse width of 5.64 ms is applied. The sub-steps 1-1, 1-2, 1-3, 2-1, 2-2, 2-3 and 3 can also be performed continuously when one scan line is selected.
The gradation level of each pixel is determined by combining the sub-steps to be turned ON. For example, for a gradation of zero, all of the sub-steps are turned ON. For a gradation level of 3, the sub-steps 1-1, 1-2, 1-3, 2-1 and 3 are turned ON and the other sub-steps are turned OFF. For a gradation level of 12, the sub-steps 1-2 and 1-3 are turned ON and the other sub-steps are turned OFF.
FIG. 5 is a diagram illustrating a configuration of the whole display device in the conventional example in which the display element 10 of simple matrix type having a display material with memory properties, such as cholesteric liquid crystal, is used. For example, the display element 10 is in conformity with the A4 size/XGA specifications and has 1,024×768 pixels. A power source 21 outputs a voltage of, for example, 3 V to 5 V. A step-up part 22 steps up an input voltage from the power source 21 to 38 V by a regulator, such as a DC-DC converter. A voltage switching part 23 generates various voltages by voltage division using a resistor etc. A voltage stabilization part 24 uses a voltage follower circuit of an operational amplifier in order to stabilize the various voltages supplied from the voltage switching part 23.
An original oscillation clock part 25 generates a base clock used as a base of the operation. A divider part 26 divides the base clock and generates various clocks necessary for the operation, to be described later.
A control circuit 27 generates a control signal based on the base clock, various clocks, and image data D and supplies it to a common driver 28 and a segment driver 29.
The common driver 28 drives 768 scan lines and the segment driver 29 drives 1,024 data lines. Because image data given to each pixel of RGB are different, the segment driver 29 drives each data line independently. The common driver 28 drives the line of RGB commonly. In the present embodiment, a driver IC uses a general-purpose STN driver that outputs two values. As a general-purpose STN driver that can be used, various drivers are available.
As described above, in the cholesteric liquid crystal display device, a voltage pulse of ±36 V having a pulse width of 40 ms is applied in the first step. In the second step, a voltage pulse of ±18.6 V having a narrow pulse width is applied to a pixel to be written. Because of this, the scan lines includes a line to which a selection voltage is applied and a line to which a non-selection voltage is applied, and the data lines include a line to which an ON voltage is applied and a line to which an OFF voltage is applied, and there are four combinations of applied voltages. It is necessary that only in a pixel corresponding to a scan line to which a selection voltage is applied and a data line to which an ON voltage is applied, the gradation be changed and not changed in other pixels. A general-purpose STN driver is configured to have voltage terminals to which four kinds of voltage V0, V21, V34 and V5 are supplied and to output a voltage pulse that satisfies the above-mentioned requirement.
FIG. 6A is a diagram illustrating voltage pulses to be output in the positive polarity and negative polarity phases of the segment driver 29 and the common driver 28.
As illustrated in FIG. 6A, the segment driver 29 is supplied with 18.6 V, 9.3 V, 9.3 V and 0 V as V0, V21S, V34S and V5 and outputs a voltage pulse with an ON voltage of V0 (18.6 V) and an OFF voltage of V34 (9.3 V) in the positive polarity phase and outputs a voltage pulse with an ON voltage of V5 (0 V) and an OFF voltage of V21 (9.3 V) in the negative polarity phase. Similarly, the common driver 28 is supplied with 18.6 V, 13.95 V, 4.65 V and 0 V as V0, V21S, V34S and V5 and outputs a voltage pulse with an ON voltage of V5 (0 V) and an OFF voltage of V21 (13.95 V) in the positive polarity phase and outputs a voltage pulse with an ON voltage of V0 (20 V) and an OFF voltage of V34 (4.65 V) in the negative polarity phase.
Because the voltage pulses described above are output from the common driver 28 and the segment driver 29, voltages as illustrated in FIG. 6B are applied to each pixel in accordance with a combination of ON/OFF voltages of the common driver 28 and the segment driver 29.
In the first step, the segment driver 29 is supplied with 36 V, 36 V, 0 V and 0 V as V0, V21S, V34S and V5 and the common driver 28 is supplied with 36 V, 36 V, 0 V and 0 V as V0, V21C, V34C and V5.
The voltage stabilization part 24 of the power source circuit outputs V5, V21S, V21C, V34S and V34C. V5 is 0 V (GND) and it does not need to be output from the voltage stabilization part 24. Consequently, the voltage stabilization part 24 of the power source circuit outputs 36 V, 36 V, 36 V, 0 V and 0 V as V5, V21S, V21C, V34S and V34C in the first step and outputs 18.6 V, 13.95 V, 9.3 V, 9.3 V and 4.65 V in the second step.
FIG. 7 is a diagram illustrating a conventional circuit configuration example of the voltage switching part 23 and the voltage stabilization part 24 and such a circuit is provided for V5, V21S, V21C, V34S and V34C, respectively. In other words, five such circuits are provided. Vout is a step-up voltage output from the step-up part 22 and 38 V. The voltage switching part 23 has a serial resistor row to generate a desired voltage by dividing Vout and an analog switch 31 that switches voltages to be output. For example, a circuit configured to generate V21C generates 36 V as a voltage A and 9.3 V as a voltage B by division using a resistor, and the analog switch 31 selects and outputs one of the voltages A and B. The voltage stabilization part 24 has an operational amplifier 32 that constitute a voltage follower circuit and realizes a high source/sink capability required by a liquid crystal driver.
FIG. 8 is a time chart illustrating the operation in the conventional liquid crystal display device illustrated in FIG. 5. Immediately before the first step is initiated, the step-up part 22 is changed from the standby state into the operating state by a step-up circuit control signal and outputs the step-up voltage Vout. The output voltage Vout from the step-up part 22 is 38 V, the same both in the first step and in the second step. When the first step is completed, the voltage switching signal is switched to another, and accordingly, the voltage to be supplied to the liquid crystal driver is switched to another.
The energy consumed in the second step accounts for about 99% of the total consumed energy in the first step and in the second step. In the second step, as described above, a voltage of 38 V is applied to the operational amplifier 32 of the five voltage stabilization parts 24 and voltages of 18.6 V, 13.95 V, 9.3 V, 9.3 V and 4.65 V are output, respectively, and therefore, more than half the energy is consumed in the operational amplifier 32. Consequently, by switching the power source voltages of the operational amplifier 32 between the first step and the second step, it is possible to reduce the consumption of energy.
For example, if it is assumed that the size of the display element 10 is A6 and the power source voltage of the operational amplifier 32 is 38 V, the same both in the first step and in the second step, while the average power consumption of the part including the operational amplifier, the common driver 28, the segment driver 29 and the display element 10 is 146 mW, the average power consumption is reduced to 85 mW when the power source voltage of the operational amplifier 32 is set to 22 V in the second step. The consumed current of the operational amplifier 32 in the standby state is 220 μA, and therefore, 1.1 mA in total for the five operational amplifiers, and while a total of the consumed current of the operational amplifier 32 in the standby state is 41.8 mW at 38 V, it is 24.2 mW at 22 V.
For a cholesteric liquid crystal display device, consumption of energy is very important because it is related to the lifetime of a battery. As described above, it is possible to reduce consumption of energy by setting the power source voltage of the operational amplifier 32 to an optimum voltage in the first step and in the second step, respectively, however, such a measure is not conventionally used. The reason for this is explained below.
There are two configurations for switching the output voltages Vout of the step-up part 22. In one configuration, the step-up part 22 is configured by a one step-up circuit and the step-up ratios of the step-up circuit are switched and in the other configuration, the step-up part 22 is configured by two step-up circuits of different output voltages and an output is selected.
FIG. 9 is a diagram illustrating a configuration of a conventional example of the step-up part 22 that has one step-up circuit and the step-up ratios are switched thereby. Reference numeral 35 represents a step-up circuit IC, for example, LT3463 (brand name) manufactured by Linear Technology Corporation. This step-up circuit IC is a step-up DC-DC converter. Reference numeral 36 is an analog switch element. Between an SW terminal and a Vout terminal of the step-up circuit IC35, a Schottky barrier diode is incorporated. The output voltage Vout is set by a voltage to be fed back to a feedback terminal FB of the step-up circuit IC35. The configuration is such that Vout is divided by two resistors, i.e., a 1,500 KΩ resistor and a 51 KΩ resistor or a 90.4 KΩ resistor selected by the analog switch element 36 and thus feedback is performed. As illustrated schematically, when the output voltage control signal is at L, the 51 KΩ resistor is selected by the analog switch element 36 and Vout changes to 38 V, and when the output voltage control signal is at H, the 90.4 KΩ resistor is selected by the analog switch element 36 and Vout changes to 22 V.
However, the step-up part 22 in FIG. 9 has a problem in that it takes a long time (settling time) for the output of the step-up circuit to reach a predetermined low voltage when the output Vout is switched from a high voltage to a low voltage. Specifically, with a 4.7 μF decoupling capacitor and a 100 KΩ discharge resistor for reducing settling time, the power consumption at the discharge resistor is 14.4 mW when Vout is 38 V and 4.8 mW when Vout is 22 V, and the settling time is 0.94 sec. In order to reduce the settling time to 0.1 sec or less, it is necessary to set the resistance value of the discharge resistor to about 1/10 and in this case, the power consumption is 135 mW when Vout is 38 V and 45 mW when Vout is 22 V, which are very large values. This makes it meaningless to reduce the consumption of energy by reducing the voltage to be applied to the operational amplifier in the second step.
In the configuration in FIG. 9, the output voltages Vout are switched by switching the voltages to be fed back by selecting the 51 KΩ resistor and 90.4 KΩ resistor by the analog switch element 36; however, because of the nonlinearity of the analog switch element 36, there arises a problem in that the step-up operation is likely to become unstable when the step-up ratio is high and Vout=38 V. In particular, it takes a considerably long time to reach a constant state after the output voltages are switched and there is a problem that noise is high.
Because of the above-mentioned reasons, in the existing circumstances, the step-up part having a configuration in which one step-up circuit illustrated in FIG. 9 is provided and its step-up ratios are switched is not used.
FIG. 10 illustrates a configuration supposed when two step-up circuits of different output voltages are provided in the step-up part 22 and an output is selected. Reference numerals 37 and 38 represent the same IC as the step-up circuit IC35 in FIG. 9 and reference numeral 39 represents an analog switch element. The step-up circuit IC 37 is set so that the feedback voltage is Vout=38 V, the step-up circuit IC 38 is set so that the feedback voltage is Vout=22 V, and the output voltage Vout=38 V of the step-up circuit IC 37 and the output voltage Vout=22 V of the step-up circuit IC38 are selected by the analog switch element 39.
In the circuit configuration in FIG. 10, the two step-up circuit ICs are used and the cost is increased accordingly; however, what brings about a problem of cost is the analog switch element 39 rather than the step-up circuit IC. The analog switch element 39 is used in a large-sized, high voltage power source, and therefore, very expensive. In order to reduce the settling time required for the output of the step-up part 22 to switch from a high voltage to a low voltage, it is indispensable to use the expensive analog switch element 39. In actuality, the analog switch element 39 is more expensive compared to the step-up circuit IC.